Ahead of his speaking appearance at Microelectronics US on April 22-23, Takuya Katayama, senior manager product management at MIPS, a GlobalFoundries company, discusses the potential of physical AI, best practices for developing and supporting functional safety platforms, and MIPS and GlobalFoundries’ vision of RISC-V at foundry scale.

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Hi, Takuya. Tell me a little bit about yourself, your career to date, and your roles and responsibilities at MIPS?

I started my professional career at Fuji Xerox in Japan as an inkjet firmware developer, and basically learned embedded systems there. Then I relocated to the US to join the company, developing printer software and hardware. Prior to joining MIPS, I was a product manager at Intel for Atom processors.

At MIPS, I’m a member of the product management team. Our Atlas Explorer brings microarchitecture simulation model to developers early in their development phase. Beyond using functional model simulations, it generates much more accurate performance data with core behaviour information that allows developers to analyse their workloads and optimise both hardware and software to the workload, rather than optimising software for the hardware. This is a significant development process change, and my focus is to emphasise how Atlas Explorer can support shift rate for a better quality product.

You’re going to be speaking at Microelectronics US on software-guided intelligence for physical AI platform design. Where are we at now with physical AI in your opinion and what can we expect in the future?

Let me go through where we are in terms of physical AI. There are three industry trends that need to be resolved; first, moving inference from the data centre to the edge; secondly, building a scalable platform based on open compute; and lastly, improving efficiency and optimising cost.

In the early days, most of the inference was handled at the data centre with high compute and high latency. It was okay to demonstrate the concept, but for the physical AI era, with the practical edge devices, especially for autonomous devices, inference needs to be at the edge for lower latency. For the edge environment, compute also needs to be lower cost and lower latency. A paper published by Mel Siegel in 2003 discussed required elements for robotics as sense, think, act and communicate. They are the areas of compute challenges for physical AI to be autonomous. Physical AI is a big opportunity for edge platforms, but it is still in the early stage, so we need to evolve ourselves to support those concepts.

One of the important subjects of the Microelectronics US event is in RISC-V and how this is developing. How is RISC-V tailored for physical AI markets as you see it, and what are the key advantages?

The builders of new physical devices want to have open standards-based technology. RISC-V is a great fit because of its openness and modular nature. RISC-V standards were developed by leaders in the technology industry, and can be extended to specific customers’ need. This adaptability is a great fit for the changing nature of AI.

What are the challenges for supporting platforms that require functional safety, such as automotive and industrial markets?

Open standards certainly helps to accelerate core development, and by having more developers working on the same standard, in collaboration with ecosystem partners, accelerates the maturity of technology. Having said that, the required effort for safety and legal of automotive, defence, industrial, are very high, and technology needs to be designed with intention to achieve the requirement. That’s where the ecosystem partners helps us too.

MIPS has a long history of developing and supporting functional safety platforms. It’s in our DNA. We’ve empowered multiple generations of advanced drivers assistance systems. Based on collaboration, we recently achieved the world’s first safety-certifiable multi-thread RISC-V processor IP. We continue to develop our portfolio to support event-driven and safety-capable applications, helping our customers achieve functional safety certifications, including ISO 26262 and the IEC 61508 certification. AI in the real world needs to be reliable and robust, which is what we are building.

A report published in October unveiled MIPS’ and GlobalFoundries’ vision of RISC-V at Foundry Scale, the convergence of open standards with enterprise-grade production discipline. Could you outline the key thoughts behind this, and what this means for the various industries you’re involved with?

RISC-V at the foundry scale is the resource to go where our customers are, both in geography, where they want to build, but also in design, where they want to support workloads. RISC-V gives MIPS the freedom to develop compute IP solutions based on those.

Recently, we have announced multiple design wins with customers in different vertical markets, from aerospace with ForwardEdge ASIC, to industry robotics with enormous semiconductors partnering with MIPS to build a physical AI platform. We support the edge market from automotive to aerospace, industry robotics to smart manufacturing and infrastructure for data centre, enterprise networking and more.

What message do you want attendees to come away with from your presentation at Microelectronics US?

In this industry, the development approach was always hardware-first. Software development starts later in the process. It is a significant risk to the programme, as a critical defect may be detected at the end of the programme, and it may cause significant performance, or financial issues, or scheduling a required workaround. This is because the developer needs to wait for RTL to become available to start to perform accurate analysis. So that was the industry standard, and MIPS is trying to change this approach significantly. Our Atlas Explorer simulates workload at the micro-architecture level, to bring a software-first approach. It allows developers to analyse more accurate performance data and core behaviour much earlier than RTM becomes available, and results can be fed back to the hardware and software design. It enables customers to build platforms with high confidence of good market fit, and achieve their efficiency and performance goals.